This invention relates to a method and system for testing a semiconductor memory device.
Semiconductor manufacturers may test the reliability of a semiconductor memory device by varying a test voltage applied to the semiconductor device over a voltage range during a test period. A cycle represents a transition of the test voltage across an entire voltage range. By varying the voltage over many cycles (e.g., greater than 100,000 cycles), the longevity of the semiconductor device may be measured. The variation of the voltage over many cycles in a controlled environment may be referred to as an accelerated life test of the semiconductor memory device.
A typical accelerated life test for semiconductor memory device, such as flash memory, involves testing for proper operation of the semiconductor memory device during program-erase voltage cycles and read voltage cycles. A total cycle duration equals the sum of a duration of one program-erase cycle, a duration of one read voltage cycle, and any intervening time between the different voltage cycles. The intervening time in the total cycle duration may be based on a typical switching speed of a conventional commercially available test fixture or a power supply where the power supply switches from a program-erase voltage level to a read voltage level. Data is written into the memory and read from the semiconductor memory device to verify proper data storage and retrieval operation.
A typical test fixture may require more than 217 days to test a one Megabyte memory device over 100,000 cycles. If each total cycle takes a total cycle duration ct (e.g., 3 milliseconds) to complete and if n (e.g., 100,000 cycles) cycles are executed, the accelerated life test would take a total duration of ct n (m/s) for a flash memory, where m is the total storage size of the memory in bytes and s in the memory sample size serviced per one total cycle duration.
The semiconductor manufacturer may not wish to ship semiconductor memory devices until proper testing is complete to assure shipment of a reliable product. If a semiconductor manufacturer could reduce the testing duration for accelerated life tests, the semiconductor manufacturer might realize improved responsiveness to customer demand for the semiconductor devices, reduced pressure to maintain inventory of the semiconductor devices to meet tight shipment schedules, and reduced manufacturing costs. Thus, a semiconductor manufacturer has a need for reducing the testing time associated with testing (e.g., accelerated life tests) of semiconductor memory devices, such as flash memory.
In accordance with the invention, a method and system for testing a semiconductor memory device applies defined test voltages to a semiconductor memory device in a manner that minimizes a time lapse during shifting from one voltage level to another or one voltage range to another. The system includes registers for storing codewords. Each codeword represents a discrete voltage level. The registers have inputs and outputs. Digital-to-analog converters are coupled to the outputs of the registers for converting a codeword into a corresponding analog voltage with a discrete voltage level. A multiplexer derives a test output voltage from the analog voltage, an external voltage, or both. A mode controller controls the derivation of the test output voltage by the multiplexer. The test output voltage is compliant with defined voltage ranges associated with corresponding modes.
In accordance with one aspect of the invention, the test device provides test voltages over three discrete ranges, including an erase mode range, a program mode range, and read mode range, in rapid succession. In accordance with another aspect of the invention, variations in the voltage within each range may be programmed as a discrete sequence or pattern of voltage steps with a resolution determined by a register controller and a digital-to-analog converter. The time for changing from one voltage step to another within a range is generally uniform. Further, the transition time from one mode range to another is minimized by using multiple, analog-to-digital converters in a coordinated manner to reduce the total time necessary to conduct testing (e.g., an accelerated life test) of a semiconductor memory device.